Various processes such as film formation, etching and the like are repeatedly performed on a semiconductor wafer to manufacture a desired semiconductor device. Recently, in order to meet demands for high-speed semiconductor device, miniaturization of a wiring pattern and high level of integration, it is required to realize low resistance of wiring (high conductivity) and high electromigration resistance.
Accordingly, copper (Cu) having a high electromigration resistance and a higher conductivity (lower resistance) has been investigated as an alternative wiring material to Al or W.
As for the Cu wiring forming method, there has been proposed a technique including: forming a barrier film formed of Ta, Ti, TaN, TiN or the like on an entire interlayer insulating film having a trench or a hole by a plasma sputtering as an example of a physical vapor deposition (PVD); forming a Cu seed film on the barrier film by the plasma sputtering; filling a trench or a hole by performing a Cu plating; and removing a residual Cu thin film or a residual barrier film remaining on the wafer surface by a chemical mechanical polishing (CMP) (see, e.g., Japanese Patent Application Publication No. 2006-148075). A PVD-TaN film attracts attention as a barrier film due to its high barrier properties.
However, along with the progress of the miniaturization of a design rule of a semiconductor device, a hole diameter or a width of a trench has reached several tens of nm, and the formation of a Cu wiring in a recess such as a small trench or a small hole leads to an increase of a wiring resistance. The low resistance of the Cu wiring can be realized by minimizing the thickness of the barrier film to increase the volume of Cu in the recess. However, when the barrier film is formed by PVD as in a conventional case, it is difficult to form a thin and conformal barrier film in the recess.